The present invention pertains generally to logic analyzer user interfaces, and more particularly to a user interface that allows simplified clock selection.
As known by those skilled in the art, a logic analyzer is an electronic instrument used to detect, analyze, and display digital voltage signals. Logic analyzers provide many configuration functions as a result of the increasing operational complexity of target devices. In many measurement applications, however, not all of the configuration functions are needed to obtain simple measurementsxe2x80x94that is, the necessary configuration functions are selected in accordance with level of measurement complexity.
Conventional logic analyzers include a graphical user interface that allows a user to make selections with respect to the configuration functions. The graphical user interface is generally made available on a display integrated with the logic analyzer, and may additionally be made available on a remote terminal that communicates with the logic analyzer. In prior art logic analyzers, the user is required to make selections with respect to all the configuration functions, even if the desired measurements do not require some of the configuration functions. The user must select a xe2x80x9cdon""t carexe2x80x9d value with respect to an unnecessary configuration function. These unnecessary configuration function setting operations are time-consuming. Furthermore, the complex array of a configuration settings renders the setup of the logic analyzer confusing to unskilled or unfamiliar users of the logic analyzer.
A logic analyzer generally allows data sampling in one of two clock modesxe2x80x94either state mode or timing mode. In a state mode measurement, the logic analyzer is clocked by a signal from the system under test. Each time the clock signal becomes valid, the analyzer samples data from the system under test. Since the analyzer is clocked by the system, state measurements are synchronous with the test system. In a timing measurement, the logic analyzer samples data at regular intervals according to a clock signal internal to the timing analyzer. Since the analyzer is clocked by a signal that is not related to the system under test, timing measurements capture traces of electrical activity over time. These measurements are asynchronous with the test system.
Clock setup must be correctly accomplished in order for a synchronous sampling (i.e., state mode) measurement to be acquired by the logic analyzer. In previous user interface implementations, the portion of the user interface which facilitates the specification of clocks has been distributed over several unrelated setup windows accessed from within the logic analyzer""s graphical user interface. A prior art graphical user interface clock setup dialog is shown in FIGS. 1 and 2.
FIG. 1(a) is a prior art logic analyzer user interface illustrating an example setup window 2 of a prior art logic analyzer. Setup window 2 comprises four tabs: Config tab 20 which allows the user to set up the measurement configuration of a machine, Format tab 40 which allows the user to setup the format in which to display the captured measurements, Trigger tab 60 which allows the user to set up the point on which data is captured, and Symbol tab 80 which allows the user to map alphanumeric symbols to raw data.
FIG. 1(a) displays the Config tab 20. The Config tab 20 selections are displayed by clicking, using a mouse, on the Config tab 20. The Config tab 20 selections tell the logic analyzer how the hardware (i.e., the available logic analyzer pods) is connected. In the illustrative embodiment, the logic analyzer allows the user to define and connect to up to two different machines, in the illustrative embodiment named MACHINE 1 and MACHINE 2. In this embodiment, the logic analyzer is capable of operating as a two-analyzer machine and represents both machines under the Config tab 20, allowing the user to rename the machines to any names desired. The assigned names are shown wherever appropriate under the other tabs to identify the associated machine settings.
Config tab 20 comprises a machine window 21 and 31 for each machine. Each machine window 21 and 31 comprises a respective name display 22 and 32 to identify its associated machine, and a respective machine type button 24 and 34 which toggles either to a timing type or a state type, or an xe2x80x9coffxe2x80x9d state in which the machine does not operate. The setting of the machine type button 24 and 34 communicates to the logic analyzer to operate either as a timing analyzer or a state analyzer. In FIG. 1(a), MACHINE 1 is set to operate in timing mode, and MACHINE 2 is set to off.
Each machine window 21 and 31 also comprises an assigned pod window 26 and 36, which displays the pods assigned to that particular machine. In the illustrative embodiment, pods A1 and A2 are assigned to MACHINE 1, and MACHINE 2 has no pods assigned to it. Each pod A1, A2, A3, A4, A5 and A6 has a clock associated with it, labeled J, K, L, M, N and P, respectively. The user assigns pods to one or the other of the two machines by selecting a pod displayed in the unassigned pod window 38 and dragging it to the assigned pod window 26 or 36 as appropriate. Activity occurring on each pin of a pod is displayed as a double arrow. No activity is displayed as a dash.
Once the machine type and assigned pods are set up, the user must obtain the format selections by clicking the Format tab 40, shown in FIG. 1(b). The format selections tell the logic analyzer how to use its internal resources Format tab 40 includes an operating mode button 51, which defines the operating mode of the machine. In the example of FIG. 1(b), MACHINE 1 is set to operate in timing mode at 333 MHz, with a memory depth of 128K samples. Format tab 40 includes a data level button 43, 53 for each assigned pod indicated by labels 42, 52, which defines the data levels of the signals received on each channel associated with the respective pod. In addition, Format tab 40 includes a set of labels 44 for bits or sets of bits that will be monitored during a measurement (also called a xe2x80x9ctracexe2x80x9d). The user may define the labels 44 associated with bits or sets of bits of the assigned pods. Each label has a clock definition control 45, a first associated pod definition control 46, and a second associated pod definition control 47. The user clicks on the desired pod definition control 45, 46, 47, which activates a pop-up menu 59 that allows the user to click on the individual bits of the ass pod definition to define which bits to monitor. The monitored bits are displayed with a xe2x80x9c*xe2x80x9d, and the un-monitored bits are displayed with a xe2x80x9c.xe2x80x9d. An activity indicator line 48 indicates which bits are active by displaying a xe2x80x9cxe2x80x9d.
Once the format of the data and clock lines are set up, the user clicks on the Trigger tab 60, shown in FIG. 1(c), to set up the trigger. A trigger is a reference event around which information is gathered. For example, in a logic analyzer, the user might wish to trigger on a glitch on a hardware line when operating in timing mode, or on an entry to a subroutine in software when operating in state mode. Logic analyzers use the trigger specification to determine when to start storing data. When beginning, the trigger might be set up on the first occurrence of any kind (trigger on xe2x80x9canystatexe2x80x9d). As the user learns more about the problem, the trigger specification might be modified to enter more specific trigger conditions. A trigger specification is a set of conditions that must be true before the instrument triggers.
Trigger tab 60 includes an xe2x80x9cArming Controlxe2x80x9d button 61 that allows the user to set up the arming sequence between the two machines MACHINE 1 and MACHINE 2. A logic analyzer machine must be armed before it can search for its trigger condition. Typically, machines are armed immediately when a xe2x80x9cRunxe2x80x9d or a xe2x80x9cGroup Runxe2x80x9d is selected. Alternatively, arming control can be used to set up one machine to arm another. In this setup, the second machine cannot search for its trigger condition until it receives the arming signal from the first machine.
A sampling period control 62 allows the user to set the period of the internal sampling clock. A trigger position control 63 allows the user to instruct the logic analyzer to store data measurements collected either leading up to the trigger event, after the trigger event, or evenly distributed before and after the trigger event.
Trigger tab 60 also includes a trigger resource definition frame 64, which includes a pattern tab 65 for setting up trigger pattern options, an edge tab 66 for defining the trigger edges, a range tab 67 for configuring the trigger ranges, and a timer tab 68 for setting up timers. In the illustrative embodiment, the Edge tab 66 is displayed. Edge tab 66 displays the configuration for two edges. Each edge configuration includes an edge name field 69, a label field 70, and a defined edge field 71. Clicking on the defined edge field 71 pops up an edge definition window 72, shown in FIG. 1(d), that includes an edge definition field 73. An edge term can be set to detect a rising edge (↑), falling edge (↓), either edge (), no edge (.), or a glitch (*) on an input signal. Once the trigger definition is configured, the trigger sequence is set up by clicking on the trigger sequence level button 77, which pops up a trigger sequence window 74, shown in FIG. 1(e). Trigger sequence window 74 includes a boolean sequence layout that allows the user to set up a boolean trigger sequence.
Symbols tab 80 allows the user to define labels that represent patterns and ranges of values found on sets of pod bits.
FIG. 2(a) displays the Config tab 20, where MACHINE 1 is set to operate in state mode, and MACHINE 2 is set to off. Again, pods A1 and A2 are assigned to MACHINE 1, and MACHINE 2 has no pods assigned to it. Clocks J and K, on pods A1 and A2, are assigned to MACHINE 1. Activity occurring on each pin of the pods are displayed as a double arrow.
Once the machine type and assigned pods are set up, the user must obtain the format selections by clicking the Format tab 40, shown in FIG. 2(b). The format selections tell the logic analyzer how to use its internal resources. Format tab 40 includes an operating mode button 51, which defines the operating mode of the machine. In the example of FIG. 2(b), MACHINE 1 is set to operate in state mode at 100 MHz, with a sample depth of 128K.
Format tab 40 includes a pod clock control button 81 and 82 for each associated pod indicated in respective labels 42 and 52. When the user clicks on a pod clock control button 81 or 82, a popup menu 83 appears to allow the user to set up the clock associated with the pod to one of either Master Clock, Slave Clock, or Demultiplex mode. In Master Only mode, data on a pod that is designated a master clock is latched and strobed into analyzer memory when the status of the master clock inputs meet the requirements of the master clocking arrangement.
In Slave Only mode, data on a pod that is designated a slave clock is latched when the status of the slave clock inputs meet the requirements of the slave clocking arrangement. Then, followed by a valid master clock, the slave data is strobed into analyzer memory along with the master data. If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to a valid master clock is strobed into analyzer memory.
Demultiplex mode is used to store two different sets of data that occur at different times on the same channels. In Demultiplex mode, only one pod of the pod pair is used, and that pod is selectable. Channel assignments are displayed as Demultiplex and Slave. Assign slave and master data to separate labels for easy recognition of the two sets of data. Both the master and slave clocks are used in the Demultiplex mode. When the analyzer sees a match between the slave clock input and the slave clock arrangement, demultiplexed slave data is latched. Then, following a valid master clock, the slave data is strobed into analyzer memory along with the master data. If multiple slave clocks occur between master clocks, only the data latched by the last slave clock prior to the master clock is strobed into analyzer memory.
Format tab 40 also includes a machine clock button 54, which allows the user to define how the machine""s data will be sampled into memory. In the example of FIG. 2(b), the machine clock is set to Master Clock. Once the machine clock is assigned one of three clock arrangements, its clock follows the configuration in the master and slave clock fields defined in a separate dialog. The machine clock button 54 and its associated clocking arrangement are only available when the machine is set up as a state analyzer.
Clicking on the machine clock button 54 pops up a master clock configuration window 84 in a separate dialog box. The master clock configuration window 84 includes buttons for setting the sampling edges of the various clocks available to the machine, along with the ability to set qualifiers Q1, Q2, Q3, Q4. This is shown in FIG. 2(c). In the example of FIG. 2(b), the master clock sets clock channel J on pod A1 to sample data on the rising edge.
FIG. 2(b) also shows a label SCOUNT 55 defined as the lower 8 channels of pod A1.
FIG. 2(d) shows the pattern tab 65 of trigger tab 60. In this example, two events EVENT3 85 and EVENT10 86 are defined as the decimal value 3 and 10 respectively. FIG. 2(e) shows the range tab 67 of trigger tab 60. In this example, a range RANGE4-9 73 is defined as the range between and including the decimal values 4 through 9.
Trigger sequence frame 76 shows the sequencing levels on trigger tab 60. In this example, the trigger sequence is set to store xe2x80x9canystatexe2x80x9d, then trigger upon the occurrence of xe2x80x9cEVENT3xe2x80x9d once, and then store only patterns matching the range RANGE4-9 or EVENT10. Each sequence xe2x80x9c1xe2x80x9d and xe2x80x9c2xe2x80x9d is set up by clicking on the respective sequence number button 77 and 78, which pops up the trigger sequence window shown in FIG. 1(e).
It is clear from the above description that the prior art logic analyzer user interface design allows great flexibility in defining Boolean combinations of clock edges and qualifiers. However, the design is problematic for several reasons.
First, the clock labels (e.g., J, K, L, and M) are abstract. The prior art user interface provides no indication of which clock belongs to which analyzer pod (i.e., the J clock is on Pod B1). This information is critical because the user needs to know which clock line is connected to the target system. However, in order to locate this information, the user must navigate to an entirely different screen (i.e., Config tab 20) in the user interface.
Second, in order to verify that the clock line has been correctly connected to the device under test, the user needs some indication that there is signal activity on a particular clock line. To locate this information in the user interface, the user must navigate to an entirely different setup screen (i.e., Format tab 40) to view the activity.
Another problem with the previous user interface implementation of the clock setup interface is the complexity of the interface. The clock setup user interface in the prior art is designed to allow very complicated Boolean combinations of edges and qualifiers to be specified. Users must navigate through the complexity of the interface necessary for allowing these advanced equations even when they are attempting to specify a very simple clock. By making it easier to set up these advanced specifications, the conventional user interface complicates the simpler and more common specifications.
Yet another problem of previous user interface designs is that the complexity of the user interface makes it necessary to place the clock setup in a separate dialog box (popup screen 54 of Format tab 40) rather than containing it on a single screen with other associated sampling options. This diminishes ease of use because it increases the amount of navigation through the user interface by the user.
Finally, when specifying both Master and Slave clocks, the complexity of the user interface of previous designs dictates that the master and slave clocks be specified in separate dialog boxes (e.g., popup screen 54 of Format tab 40). This makes it very difficult to see the resulting equations until setup is complete.
Accordingly, a need exists for a more straightforward user interface for a logic analyzer which allows simplicity in clock setup.
The present invention is a novel user interface for a logic analyzer that allows for simplified clock configuration selection. The graphical user interface consolidates all clock selection functions onto a single screen, allowing for ease of understanding and navigation.
In accordance with the invention, the graphical user interface is operative to receive and interpret logic analyzer signals to display logic analyzer information for a user, and to receive and interpret user input to configure the logic analyzer in accordance with the user input. The graphical user interface comprises a clock specification grid that consolidates all the clock setup configuration functions onto one user screen. The clock specification grid includes a pod identifier section comprising a plurality of pod labels, each of which corresponds to a physical pod of the logic analyzer that has a clock line. Each pod label identifies a respective pod name of its respective corresponding analyzer pod. Preferably, each of the pod labels is color coded to match the color of the label on the physical pod at the end of each logic analyzer cable. The clock specification grid includes a clock identifier section that includes a plurality of clock labels, each of which corresponds to one of the analyzer pods. The clock specification grid also includes an activity indicator section that comprises a plurality of activity indicators that indicate whether there is activity present on the clock associated with the respective analyzer pod. The clock specification grid also includes a master clock selection section. When operating in a normal mode, the master clock selection section includes a plurality of master clock selection buttons, each of which corresponds to one of the analyzer pods and allows the user to select a clock edge on which the associated clock operates. The master clock selection buttons offer the option of setting up the respective clock to be Off, Rising Edge, Falling Edge, Both Edges, Qualifier-High, or Qualifier-Low. Preferably, the master clock selection button displays the selected clock selection option. When operating in advanced clocking mode, the master clock selection section is a single master clock selection button that pops up an advanced clock selection window when clicked.
Preferably, the graphical user interface implements, among other features, a clock setup frame that contains the clock specification grid, along with a clock mode control that allows the user to set the logic analyzer clock mode. When selected, the clock mode determines the options presented in the clock specification grid.
Preferably, the graphical user interface implements a acquisition mode control frame comprising the clock setup frame and an operating mode button that defines the operating mode of the logic analyzer machine, which may be set up as at least either a state mode or a timing mode.
The simplified clock setup user interface of the invention provides several advantages over the prior art. First, the grid layout of the clocks and their setting used in the simplified clock setup user interface presents all of the pertinent information, including the pod number, its associated clock label, clock activity and the edge or qualifier selection, to the user in a single place, thereby allowing the clock setup to be more efficient over previous implementations of the clock setup which required the user to extract important information from multiple screens. Second, the layout of the user interface allows the user to build both simple and more complicated equations but does not highlight complex settings at the cost of simple settings. This overcomes the problems of the previous implementation layouts, which allowed the user to build both simple and complex settings at the cost of simple settings. By presenting all of the clock setup options all of the time, the previous implementations of clock setup user interfaces highlighted the advanced complexity that was possible and, in the process, over complicated the simpler more common specifications. Third, the efficient use of screen space by the invention allows for more information to be displayed but in a small enough space that an additional screen is not necessary. Thus, the simplified clock setup user interface can be displayed on a signal screen along with additional measurement sampling options to thereby simplify navigation. In addition, this new design allows for the display of significantly more pertinent information in a fraction of the space required by the previous implementations. This overcomes the complexity of the previous designs that made it necessary for the clock setup options to be contained in their own separate dialog. Fourth, because of the increased efficiency in the usage of screen space, the simplified clock setup user interface allows the Master and Slave clock setup to be displayed simultaneously on the same screen rather than performed in separate dialogs as in the prior art.
Accordingly, a user can confirm clock activity and verify which clock label is associated with which analyzer pod without navigating to a different screen. In addition, color-coding is preferably used to reinforce the relationship between the pod label in the user interface and the physical logic analyzer pod. Additionally, a user can quickly specify the clock settings within a single screen. An additional dialog only needs to be opened when very complicated specifications are necessary. Another advantage provided by the invention is that the compact space requirements for simplified clock setup user interface allows it to be placed on the same screen as other associated sampling options. Finally, the Simplified Clock Setup design allows a much cleaner, more intuitive presentation of information and options.